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Reference #:
2004-235
Inventors/Contributors
James S. Humble, Rick A. Philpott, Patrick J. Zabinski
Description
The fully differential circuit in a SiGe BiCMOS process accepts an input clock with duty cycle error and outputs a clock with corrected duty cycle. The desired duty cycle of the output clock is adjustable via four DC selection bits.
Patent Status
Pending |
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Contact
Bruce R. Kline, Licensing Manager
kline.bruce1@mayo.edu
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Mayo Foundation for Medical Education and Research
Office of Technology Commercialization
Centerplace 4
200 First Street SW
Rochester, MN 55905
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Phone: (507) 266-4586
Fax: (507) 284-5410
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